The present invention relates generally to semiconductor devices and more particularly to a semiconductor memory device having a parallel test mode in which data can be read out in parallel.
A semiconductor memory device, such as a synchronous dynamic random access memory (SDRAM), can be arranged into a plurality of banks. Each bank can operate as an independent memory that can be activated and have data accessed at external data terminals, which may be shared by each bank. For example, an SDRAM may be a X16, in which a 16-bit wide data word may be accessed (read or write) at one time at the external data terminals. Because the 16-bits of data can come from any of the independently operating banks, each bank must be capable of providing 16-bits of data. If the SDRAM has four banks, then internally, there can be at least 64-bits of data being accessed at one time if all the banks are activated, but only 16 of those bits may be accessed externally due to the number of external data terminals (16 in this case).
Thus, if all 64-bits of data are to be read out on the external data terminals, four separate read operations must take place.
Every semiconductor memory device that is produced should be tested to ensure that all addressable bit locations in the memory are functional. Any increase in throughput can reduce the test time, and can decrease the manufacturing costs of the device. In order to decrease test time, a parallel test operation has been developed.
In a parallel test operation, each bank can be simultaneously activated and data can be read out from each bank. Data can be compared on chip and a comparison result can be output on the external data terminals. In this way, 16-bits from each bank and thus 64-bits of data can be tested in a single read operation. This improves the efficiency of the testing of each semiconductor memory device, which can reduce the overall manufacturing cost.
When using the above-mentioned conventional parallel test mode, all the banks are simultaneously activated. This can cause increased current spikes as compared to normal operations, which can cause internal noise on the power bussing, especially during the simultaneous operation of sense amplifiers. These affects can reduce the integrity of the parallel test results.
The above-mentioned affects can be reduced by operating the test under xe2x80x9crelaxedxe2x80x9d timing conditions, such as increasing the delay time (tRCD) from a row address strobe (RAS) to column address strobe (CAS). This increases the time delay from latching a row address and activating the banks to latching a column address and selecting data to be compared and outputting the result. By doing this, the sense amplifiers can have an increased time to properly sense data. However, by operating under xe2x80x9crelaxedxe2x80x9d timing conditions, the test time is increased and the test throughput decreases which can increase the overall manufacturing cost.
Parallel test mode of operation can also be used during a burn-in test. In a burn-in test, a large number of devices are tested in parallel and can be under extreme conditions. This can be used to determine the infant mortality. When such a large number of devices are tested in parallel, increased current consumption caused by the conventional parallel test operation can generate an excessive peak current on the power source burn-in test equipment. This can reduce the integrity of the bum-in test data.
In view of the above discussion, it would be desirable to provide a semiconductor device having a reduced peak current consumption and noise generation during sensing. It would also be desirable to decrease the current consumption and noise generation during a parallel test operation.
According to the present embodiments, a semiconductor device having a normal mode of operation and a test mode of operation is provided. The semiconductor memory may include a memory cell array having a plurality of memory cell plates. In a normal mode of operation a plurality of plates may be activated. In the test mode of operation fewer plates may be activated than in the normal mode of operation.
According to one aspect of the embodiments, the plurality of memory cell plates may be a row of memory cell plates coupled to a main word line disposed in a row direction.
According to another aspect of the embodiments, a sub-word driver may receive a main word line. The sub-word driver may activate a sub-word line in a memory cell plate. In the test mode of operation fewer plates have activated sub-word lines than in the normal mode of operation.
According to another aspect of the embodiments, each memory cell plate may have a first sub-word driver and a second sub-word driver. The second sub-word driver can be on an opposite end of the memory cell plate than the first sub-word driver.
According to another aspect of the embodiments, a decoder circuit can receive a plurality of row address signals and may provide a sub-word line select signal to a sub-word driver. The first sub-word driver of a memory cell plate may be coupled to the same decoder circuit as the second sub-word driver in an adjacent memory cell plate.
According to another aspect of the embodiments, the decoder circuit can be coupled to receive a test mode signal and at least one test control signal. The at least one test control signal can indicate which memory cell plates can be activated in the test mode of operation. The at least one test control signal can have a logic value indicating a logic value of at least one external signal.
According to another aspect of the embodiments, the external signal generating the test control signal may be a data mask signal. The external signal may be sampled at approximately the same time as external row address signals are sampled.
According to another aspect of the embodiments, the memory cell array can include a plurality of rows of memory cell plates.
According to another aspect of the embodiments, the memory cell array may activate at least one of the plurality of rows of memory cell plates in a normal mode. The memory cell array may activate only a portion of at least one of the plurality of rows of memory cell plates in a test mode.
According to another aspect of the embodiments, the row of memory cell plates may be divided into a first group of memory cell plates and a second group of memory cell plates. A group signal may indicate which group of memory cell plates is to be activated in a test mode of operation.
According to another aspect of the embodiments, each memory cell plate in a row of memory cell plates may be coupled to a sense amplifier activation circuit. The sense amplifier activation circuit may be coupled to receive a test mode signal and a test control signal.
According to another aspect of the embodiments, the sense amplifier activation circuit may also be coupled to receiving a row address signal. Sense amplifier activation circuits receive a row address signal may form an exclusive OR/NOR logic function with the test control signal.
According to another aspect of the embodiments, adjacent memory cell plates may be activated in the test mode of operation.